The present invention relates to automatic test equipment ("ATE") testers for testing circuits, such as testers for testing integrated circuits. Some such testers have a processor-per-pin architecture, as described, for example, in commonly-owned U.S. Pat. Nos. 5,212,443 and 5,673,275, the disclosures of which are incorporated by reference.
In a processor-per-pin architecture, a tester has local sequencers, each of which is programmable to apply events to a terminal of a circuit under test, generally referred to as a pin of a device under test (a "DUT"). In a tester of this kind, each local sequencer generates events with reference to a global clock and other global signals. Characteristically, each local sequencer is individually programmable so that different local sequencers can provide different events during the same test period.
Generally, events are of one of two event types: drive events drive the pin to a particular state, and strobe events (also called test events) test the state of the pin. For example, a test-for-high event (which may be denoted "T1") is a strobe event that generates a logical pass-fail value indicating whether the voltage at the pin is above a threshold value that defines a high state (that is, that defines a "1"). The event time of an event specifies when the event is to occur. For a strobe event, the event may occur over a time window, testing whether the state occurs at any time in the window, or it may be an edge event, testing the state at a particular time.